Project Title: Enhanced Power Pilot Line
Project acronym: EPPL
A competitive European semiconductor industry is vital for finding solutions to the Grand Challenges identified by the European Commission. EPPL aims at making a decisive step forward to strengthen Europe’s leading position in power semiconductor technologies and More-than-Moore manufacturing capabilities, relating in particular to possibly energy-efficient electronic solutions. 2nd generation power semiconductor devices fabricated in European leading pilot lines based on 300mm wafer production are at the heart of the project, for which manufacturing excellence, cost competitiveness and challenging applications are critical boundary conditions.
The central goal of EPPL is to extend the leading position of power semiconductors “Made in Europe”. The expected improvement addresses technical challenges as well as commercial competitiveness, both in technology research, semiconductor manufacturing, chip/package interconnection technologies and energy efficient applications. A range of unique manufacturing processes and a multitude of product innovations of direct impact onto everyday high-tech life are expected, e.g. eco-friendly generation of solar power, extended ranges in automotive mobility, lower power consumption in illumination or smarter and more powerful medical-diagnostic appliances.
The project will deal with challenges related to process and production technologies, as well as advanced power metallization technologies and dedicated manufacturing processes for thin 300mm wafers:
- Research on next generation of advanced power semiconductor technologies fabricated on 300mm wafers.
- Identify and optimize relevant power semiconductor characteristics taking into account demonstrator application requirements of strategic importance.
- Setting up a pilot line for next generation power semiconductor production on 300 mm wafers combining at least two European production sites.
- Prove reliability and initial yield targets of the power semiconductor pilot line .
- Achieve best-in-class productivity in manufacturing leading-edge power semiconductors for advanced, energy efficient industrial, medical and mobility applications.
- Optimize chip-to-package interfacing stack for advanced 3D integration capabilities including a 3D pilot line setup for Si interposer.
- Strengthen European intellectual property in semiconductor technology, manufacturing and assembly.
Global responsibilities will thus be shared in a pilot line stretching across several European countries.
The project has a total budget of 75M€. It has a duration of 36 months, it will be implemented from April 2013 to March 2016 and joins a consortium of 26 partners (academic and industrial), including the major industrial players in the European semiconductor industry.
The work performed in the project EPPL is co-funded by grants from Austria, Germany, The Netherlands, Italy, France, Portugal and the ENIAC Joint Undertaking.