Nanoelectronics Back-end process for integration of nano-devices on CMOS wafers

The use of nano-devices in CMOS designs or wafers require that mixed-signal design engineers require the availability of models and electrical characteristics that represent the most accurate physical behaviour of devices. The aim of this project is to define a set of rules and electrical models to allow CMOS designers to integrate the devices produced at INL. This set of rules will depend on the specific features of each device. In addition, independent test structures will be defined to monitor the integration process. This will provide the capability to characterize the devices integrated in CMOS independently of CMOS process and circuits.

Once these models are available and delivered under the format of a design kit, the scientific and university community would be able to use the nano-fabrication capabilities at INL for their research activities